ACX_LN00 - AC, EXTEST, LVDS, unreferenced, No Defect * File name constructed as follows: * ACH_ = AC coupled High freq, ACL_ = AC coupled low freq, DC_ = DC coupled * ACX_ = AC coupled EXTEST, DCX_ = DC coupled EXTEST * L = LVDS, P = PECL, H = HSTL, others as models are provided * N = unreferenced, V = VREF center tapped * nn = defect number. See switches below. * Jeremy Castro 7/31/2001 * Carl F. Barnhart, 8/09/2001 Original setup. * Carl F. Barnhart, 8/15/2001 Set up for different SA12E parts. * Carl F. Barnhart, 8/29/2001 Modifed for changes from 8/28 meeting * Carl F. Barnhart, 11/8/2001 Modifed for changes from 11/3 meeting *============================================================================ * Run Parameters and Controls Section *---------------------------------------------------------------------------- .options post list node acct nopage .opt dvdt=3 *opt brief .opt gshunt=1e-10 .options converge=1 gmindc=1e-10 $ per request of simulator *---------------------------------------------------------------------------- * ".inc" encrypted models are in directory from which HSpice was invoked *---------------------------------------------------------------------------- .option search = './ ' .model dummy nmos level=49 version=3.1 *---------------------------------------------------------------------------- * Simulation fixed parameters (These should NOT normally be varied.) *---------------------------------------------------------------------------- .temp 25 .param sigma = 0.0 .param pvdd = 2.5 $ Chip Supply .param ps = .00001 $ Closed switch .param po = 100x $ Open switch .param fcaphi = 20000p $ Large cap for "High Freq" sim (RC=1000ns) .param fcaplo = 200p $ Small cap for "Low Freq" sim (RC=10ns) .param termp = 50 $ Termination resistor to Pad+ .param termn = 50 $ Termination resistor to Pad- .param biasp = 10000 $ Bias/recovery resistor to Pad+ .param biasn = 10000 $ Bias/recovery resistor to Pad- .param vcomcap = 10p $ cap for Vcom recovery in DC mode (RC=5ns) .param delr = 3000 $ Test Buffer input resistor .param delc = 5p $ Test buffer delay capacitor, RC=15ns .param edgev = .12 $ edge-detector hysteresis .param deltv = .08 $ delta detector hysteresis *============================================================================ * SIMULATION VARIABLES AND SWITCHES *---------------------------------------------------------------------------- * >>> Steps for setting up a specific instance for simulation: <<< *---------------------------------------------------------------------------- * 1) Change first line of file to be properly descriptive. * 2) Set parameters in this block: * swdc/swac for DC or AC operation. * coupling cap value for "high" or "low" frequency. * swvref for type of termination. * I/O, termination, and shorts voltages * bias resistances * defect switches as open or short to select defect. * 3) In the Simulation Structure, below. Search for >>>, and * Uncomment the required driver(s) and receiver(s). * Uncomment appropriate simulation duration (last statement). *---------------------------------------------------------------------------- * AC/DC coupling option .param swdc = po $ AC (po) or DC (ps) mode .param swac = ps $ AC (ps) or DC (po) mode * AC_EXTEST/EXTEST option .param swax = po $ AC_EXTEST (ps) or EXTEST (po) mode .param swex = ps $ AC_EXTEST (po) or EXTEST (ps) mode .param tup = 1us $ AC_EXTEST=99.8ns or EXTEST=1us .param tcyc = 2us $ AC_EXTEST=200ns or EXTEST=2us * Coupling Capacitor .param coupler = fcaplo $ fcaphi or fcaplo * Termination Options (po) = unreferenced .param swvref = po $ (ps) = Center Tap to Vtt * I/O book supply voltage (LVDS=2.5, PECL=3.3, HSTL=1.5) .param pvdd2 = 2.5 * Termination Center Tap voltage (Vtt: LVDS=1.2, PECL=2.0, HSTL=.75) .param pvtt = 1.2 * Voltage for "short to rail?" .param pvdd3 = 2.5 $ Shorts target * Open Defects (normally shorted switches) .param sw1 = ps $ Tx1+ Open .param sw2 = ps $ Rx1+, TxRx1+ Open .param sw3 = ps $ Rx1+, TxRx1+ Open after term .param sw14 = ps $ Rx1+_Term, TxRx1+_Term Open/Missing * Short defects (normally open switches) .param sw4 = po $ Tx1+_Vdd Short .param sw5 = po $ Tx1+_Gnd Short .param sw6 = po $ Tx1+_Tx1- Short .param sw7 = po $ Tx1+_Rx1+ Short .param sw8 = po $ Tx1+_Rx1- Short .param sw9 = po $ Rx1+_Vdd Short .param sw10 = po $ Rx1+_Gnd Short .param sw11 = po $ Rx1+_Rx1- Short .param sw12 = po $ Tx1+_TxRx5 Short .param sw13 = po $ Rx1+_TxRx5 Short * END SIMULATION VARIABLES AND SWITCHES *---------------------------------------------------------------------------- *============================================================================ *SIMULATION STRUCTURE (change ONLY where flagged with >>>) *============================================================================ *---------------------------------------------------------------------------- * Power Supplies *---------------------------------------------------------------------------- Vpwr cardvdd gnd pvdd Vpwr2 cardvdd2 gnd pvdd2 Vgnd cardgnd gnd 0 Vrail Railp gnd pvdd3 Vterm Termv gnd pvtt *============================================================================ * Drivers, Channels, and functional Receivers *---------------------------------------------------------------------------- * LVDS * >>> Uncomment entire block for use, re-comment if not used. *---------------------------------------------------------------------------- * Driver Input Signal * input node ref.node low hi delay rise fall up period vdrv1in D1 cardgnd pulse (0 pvdd 100ns 0.2ns 0.2ns tup tcyc ) *SUBCKT GND VDD A DI LT PAD PADN RG RI TS Z ZDI ZRI BLVDS_A xdriver1 cardgnd cardvdd D1 cardvdd cardgnd tx1p_1 tx1n_1 cardgnd cardvdd cardvdd z1 zdi1d zri1d BLVDS_A cz1 z1 cardgnd .1p czdi1d zdi1d cardgnd .1p czri1d zri1d cardgnd .1p * LVDS, AC-coupled should be DC terminated at source R92 tx1p_1 lvds swac R93 lvds tx1n_1 100 *SUBCKT GND VDD A DI LT PAD PADN RG RI TS Z ZDI ZRI BLVDS_A xreceiver1 cardgnd cardvdd cardgnd cardvdd cardgnd rx1p_3 rx1n cardvdd cardvdd cardgnd zrec1 zdi1r zri1r BLVDS_A czrec1 zrec1 cardgnd .1p czdi1r zdi1r cardgnd .1p czri1r zri1r cardgnd .1p *---------------------------------------------------------------------------- * PECL (3.3V LVPECL) * >>> Uncomment entire block for use, re-comment if not used. *---------------------------------------------------------------------------- * * Driver Input Signal * * input node ref.node low hi delay rise fall up period $5MHz * vdrv1in D1 cardgnd pulse (0 pvdd 100ns 0.2ns 0.2ns tup tcyc) * *SUBCKT GND VDD A DI PAD PADN RG RI TS VDD330 Z ZDI ZRI OPECL_A * xdriver1 cardgnd cardvdd D1 cardvdd tx1p_1 tx1n_1 cardgnd cardvdd cardvdd cardvdd2 z1 zdi1d zri1d OPECL_A * cz1 z1 cardgnd .1p * czdi1d zdi1d cardgnd .1p * czri1d zri1d cardgnd .1p * * Source DC termination built-in. * *SUBCKT GND VDD A DI LT PAD PADN RI TS Z ZDI ZRI IPECL_A * xreceiver1 cardgnd cardvdd cardgnd cardvdd cardgnd rx1p_3 rx1n cardvdd cardgnd zrec1 zdi1r zri1r IPECL_A * czrec1 zrec1 cardgnd .1p * czdi1r zdi1r cardgnd .1p * czri1r zri1r cardgnd .1p *---------------------------------------------------------------------------- * HSTL * >>> Uncomment entire block for use, re-comment if not used. *---------------------------------------------------------------------------- * * Driver Input Signal * * input node ref.node low hi delay rise fall up period $5MHz * vdrv1ina D1 cardgnd pulse (0 pvdd 100ns 0.2ns 0.2ns tup tcyc) * vdrv1inb D1n cardgnd pulse (0 pvdd 0ns 0.2ns 0.2ns tup tcyc) * *SUBCKT GND VDD A DI LT PAD RG RI TS VDD150 VREF Z ZDI ZRI BHSTLC1_A * xdriver1a cardgnd cardvdd D1 cardvdd cardgnd tx1p_1 cardvdd cardgnd cardvdd cardvdd2 termv z1a zdi1da zri1da BHSTLC1_A * xdriver1b cardgnd cardvdd D1n cardvdd cardgnd tx1n_1 cardvdd cardgnd cardvdd cardvdd2 termv z1b zdi1db zri1db BHSTLC1_A * cz1a z1a cardgnd .1p * czdi1da zdi1da cardgnd .1p * czri1da zri1da cardgnd .1p * cz1b z1b cardgnd .1p * czdi1db zdi1db cardgnd .1p * czri1db zri1db cardgnd .1p * *SUBCKT GND VDD A DI LT PAD PADN RI TS Z ZDI ZRI IHSTL_A * xreceiver1 cardgnd cardvdd cardgnd cardvdd cardgnd rx1p_3 rx1n cardvdd cardgnd zrec1 zdi1r zri1r IHSTL_A * czrec1 zrec1 cardgnd .1p * czdi1r zdi1r cardgnd .1p * czri1r zri1r cardgnd .1p *---------------------------------------------------------------------------- * CMOS, for shorts testing, * >>> Uncomment entire block only if sw12 or sw13 is set on (ps). *---------------------------------------------------------------------------- * * Static Driver Input Signal * vdrv5in D5 cardgnd pvdd $ Set to pvdd or 0 * *SUBCKT GND VDD A DI PAD RG RI TS Z ZDI ZH ZRI BC2550_A * xdriver5 cardgnd cardvdd D5 cardvdd txrx5 cardgnd cardvdd cardvdd z5d zdi5d zh5d zri5d BC2550_A * cz5d z5d cardgnd .1p * czdi5d zdi5d cardgnd .1p * czh5d zh5d cardgnd .1p * czri5d zri5d cardgnd .1p * *SUBCKT GND VDD A DI PAD RG RI TS Z ZDI ZH ZRI BC2550_A * xreceiver2 cardgnd cardvdd cardgnd cardvdd txrx5 cardvdd cardvdd cardgnd z5r zdi5r zh5r zri5r BC2550_A * czrec5 z5r cardgnd .1p * czdi5r zdi5r cardgnd .1p * czh5r zh5r cardgnd .1p * czri5r zri5r cardgnd .1p * R12 tx1n_1 txrx5 sw12 * R13 rx1n txrx5 sw13 *---------------------------------------------------------------------------- * Board Circuit passives (incl switches) *---------------------------------------------------------------------------- * Defect Switches R1 tx1p_1 tx1p_2 sw1 R2 rx1p_1 rx1p_2 sw2 R3 rx1p_2 rx1p_3 sw3 R4 Railp tx1p_2 sw4 R5 tx1p_2 cardgnd sw5 R6 tx1p_2 tx1n_1 sw6 R7 tx1p_2 rx1p_1 sw7 R8 tx1p_2 rx1n sw8 R9 Railp rx1p_1 sw9 R10 rx1p_1 cardgnd sw10 R11 rx1p_1 rx1n sw11 R14 rx1p_2 Ntermp sw14 * Transmission Lines Tp Tx1p_2 cardgnd Tx1p_3 cardgnd Z0=50 TD=6n L=.5 $ 6ns/meter, .5 meter Tn Tx1n_1 cardgnd Tx1n_2 cardgnd Z0=50 TD=6n L=.5 $ 6ns/meter, .5 meter * Coupling capacitors and DC switches C1 tx1p_3 rx1p_1 coupler R90 tx1p_3 rx1p_1 swdc C2 tx1n_2 rx1n coupler R91 tx1n_2 rx1n swdc * Termination R20 Ntermp Nvterm termp R21 rx1n Nvterm termn R22 Termv Nvterm swvref * Bias network R25 rx1p_2 Nvcom biasp R26 rx1n Nvcom biasn R27 Termv NVcom swac R28 vcap NVcom swdc C20 vcap cardgnd vcomcap *============================================================================ * Test receiver circuit (single ideal comparators with hysteresis) *---------------------------------------------------------------------------- * Compare reference circuit R31 rx1p_3 acxcp delr R33 acxcp ninnp swax $ Switch, closed for AC_EXTEST, open for EXTEST R35 Termv ninnp swex $ Switch, open for AC_EXTEST, closed for EXTEST C31 cardgnd ninnp delc R32 rx1n acxcn delr R34 acxcn ninnn swax $ Switch, closed for AC_EXTEST, open for EXTEST R36 Termv ninnn swex $ Switch, open for AC_EXTEST, closed for EXTEST C32 cardgnd ninnn delc * Ideal comparators with offset * * Voltage offsets (for hysteresis) * +node -node Vofstp1 rx1p_3 ofstpp edgev Vofstp2 ofstnp rx1p_3 edgev Vofstn1 rx1n ofstpn edgev Vofstn2 ofstnn rx1n edgev Vofstd1 rx1p_3 ofstpd deltv Vofstd2 rx1n ofstnd deltv * amplifier with clipping (simple comparator) * out+ out- PWL(1) in1+ in1- Gain = 125 initial ecmpps testps cardgnd PWL(1) ofstpp ninnp -10,0 -20m,0 -10m,.01 0,1.25 10m,2.49 20m,2.5 10,2.5 ic=2.5 ecmppr testpr cardgnd PWL(1) ninnp ofstnp -10,0 -20m,0 -10m,.01 0,1.25 10m,2.49 20m,2.5 10,2.5 ic=2.5 ecmpns testns cardgnd PWL(1) ofstpn ninnn -10,0 -20m,0 -10m,.01 0,1.25 10m,2.49 20m,2.5 10,2.5 ic=2.5 ecmpnr testnr cardgnd PWL(1) ninnn ofstnn -10,0 -20m,0 -10m,.01 0,1.25 10m,2.49 20m,2.5 10,2.5 ic=2.5 ecmpds testds cardgnd PWL(1) ofstpd rx1n -10,0 -20m,0 -10m,.01 0,1.25 10m,2.49 20m,2.5 10,2.5 ic=2.5 ecmpdr testdr cardgnd PWL(1) ofstnd rx1p_3 -10,0 -20m,0 -10m,.01 0,1.25 10m,2.49 20m,2.5 10,2.5 ic=2.5 * Dummy loads ccmp1s testps cardgnd .1p ccmp1r testpr cardgnd .1p ccmp2s testns cardgnd .1p ccmp2r testnr cardgnd .1p ccmp3s testds cardgnd .1p ccmp3r testdr cardgnd .1p * For plotting only, no functional use * out+ out- in+ in- gain Edif1 diffp cardgnd rx1p_3 ninnp 1.0 Edif2 diffn cardgnd rx1n ninnn 1.0 Edif3 diffd cardgnd rx1p_3 rx1n 1.0 * Dummy loads cdifp diffp cardgnd .1p cdifn diffn cardgnd .1p cdifd diffd cardgnd .1p *============================================================================ * Type of analysis, output increment, duration * >>> Set for low frequency or for high frequency *---------------------------------------------------------------------------- *.tran 0.2n 10000n $ High Frequency (initial conditions must die out) *.tran 0.1n 1000n $ Low frequency .tran 0.5n 2us $ EXTEST *---------------------------------------------------------------------------- * Additional Simulation runs *---------------------------------------------------------------------------- .alter "ACX_LN01 - AC, EXTEST, LVDS, unreferenced, Tx1p open" .param sw1 = po $ Tx1+ Open .alter "ACX_LN02 - AC, EXTEST, LVDS, unreferenced, Rx1p open" .param sw1 = ps $ Tx1+ Open .param sw2 = po $ Rx1+ Open .alter "ACX_LN03 - AC, EXTEST, LVDS, unreferenced, Rx1p open after term" .param sw2 = ps $ Rx1+ Open .param sw3 = po $ Rx1+, TxRx1+ Open after term .alter "ACX_LN04 - AC, EXTEST, LVDS, unreferenced, Tx1p<=>Vdd" .param sw3 = ps $ Rx1+, TxRx1+ Open after term .param sw4 = ps $ Tx1+_Vdd Short .alter "ACX_LN05 - AC, EXTEST, LVDS, unreferenced, Tx1p<=>Gnd" .param sw4 = po $ Tx1+_Vdd Short .param sw5 = ps $ Tx1+_Gnd Short .alter "ACX_LN06 - AC, EXTEST, LVDS, unreferenced, Tx1p<=>Tx1n" .param sw5 = po $ Tx1+_Gnd Short .param sw6 = ps $ Tx1+_Tx1- Short .alter "ACX_LN07 - AC, EXTEST, LVDS, unreferenced, Tx1p<=>Rx1p" .param sw6 = po $ Tx1+_Tx1- Short .param sw7 = ps $ Tx1+_Rx1+ Short .alter "ACX_LN08 - AC, EXTEST, LVDS, unreferenced, Tx1p<=>Rx1n" .param sw7 = po $ Tx1+_Rx1+ Short .param sw8 = ps $ Tx1+_Rx1- Short .alter "ACX_LN09 - AC, EXTEST, LVDS, unreferenced, Rx1p<=>Vdd" .param sw8 = po $ Tx1+_Rx1- Short .param sw9 = ps $ Rx1+_Vdd Short .alter "ACX_LN10 - AC, EXTEST, LVDS, unreferenced, Rx1p<=>Gnd" .param sw9 = po $ Rx1+_Vdd Short .param sw10 = ps $ Rx1+_Gnd Short .alter "ACX_LN11 - AC, EXTEST, LVDS, unreferenced, Rx1p<=>Rx1n" .param sw10 = po $ Rx1+_Gnd Short .param sw11 = ps $ Rx1+_Rx1- Short .alter "ACX_LN14 - AC, EXTEST, LVDS, unreferenced, Term Open" .param sw11 = po $ Rx1+_Rx1- Short .param sw14 = po $ Termination Open .END