P1149.6 Simulation Results by Defect

The results are listed by defect here. This is to facilitate an ivestigation of how a single defect is handled by different I/O protocols, termination schemes, and coupling capacitor ranges.

To find a specific simulation instance, select the defect type from the list below. That will give you a page listing the coupling, test mode, termination, and technology. where you can select the specific simulation.

A final note: all plots are auto-scaled, so pay attention to the scales! Some plots show very robust signals until you realize the scale is in microvolts.

• 00: No Defect.

Open type defects:

• 01: Tx1+ Open Driver positive leg open (before the capacitor).
• 02: Rx1+ Open before term. Receiver positive leg open between capacitor and terminator.
• 03: Rx1+ Open after term. Receiver positive leg open between terminator and receiver.
• 14: Term+ Open Termination Resistor open to receiver positive leg.

Short type defects:

• 04: Tx1+<=>Vdd Driver positive leg shorted to Vdd.
• 05: Tx1+<=>Gnd Driver positive leg shorted to Ground.
• 06: Tx1+<=>Tx1- Driver positive leg shorted to driver negative leg (shorted driver).
• 07: Tx1+<=>Rx1+ Driver positive leg shorted to receiver positive leg (shorted capacitor).
• 08: Tx1+<=>Rx1- Driver positive leg shorted to receiver negative leg.
• 09: Rx1+<=>Vdd Receiver positive leg shorted to Vdd.
• 10: Rx1+<=>Gnd Receiver positive leg shorted to Ground.
• 11: Rx1+<=>Rx1- Receiver positive leg shorted to receiver negative leg (shorted receiver).
• 12: Tx1-<=>TxRx5 Driver negative leg shorted to other net (CMOS BIDI).
• 13: Rx1-<=>TxRx5 Receiver negative leg shorted to other net (CMOS BIDI).