P1149.6 Simulation Results Database

We intend for there to be simulations for every combination of the following parameters, but may not quite make it:

• I/O Protocols: CML (Bipolar only, so far), LVDS, and LVPECL.
• Coupling Mode:
  • AC coupled at high frequency (Thp=10*Ttest),
  • AC coupled at low frequency (min Thp per Chapter 6, or 10*Thp=Ttest),
  • AC coupled at high frequency with the termination before the coupling,
  • DC coupled AC_EXTEST,
  • AC and DC coupled EXTEST.
• Termination:
  • Un-referenced,
  • Center tapped to a reference voltage (Vref),
  • and "On-Chip" terminated/coupled (termination resistor before very small caps, no low-pass filter).
• No defect, plus 14 defects as defined in the Chip Tiger Team documentation.

The calculations, based on the P1149.6 Proposed Standard (Version 3.0f), Chapter 6, are presented here and on the "Technology, ..." page below:

• for LVDS;
• for LVPECL.

The simulations are organized for access two ways:

• by Technology, Termination, and Coupling to compare the behavior of all defects for any one combination, and
• by Defect type to compare how a single defect type behaves for various combinations of technology, termination and coupling.

General Information on the simulations.

WHATS NEW? Many of the simulations were rerun with a Test Receiver model modified to conform to Chapter 6 parameters. The model still does not have the hysteretic memory in order to examine the "set" and "reset" behavior. The replacement simulations are flagged with . Specific updates included in those simulations include:

• The Test Receiver is modelled as an idealized amplifier with two amplification stages and a single RC pole between them to model the Thyst slew-rate limit.
• Power supply noise has been added to the driver to emulate noise that might occur at UpdateDR. I have not added noise to the receiver side as I do not think it will have any effect on the test receiver idealized model. Detailed simulation plots of the power supply noise (all on Vss, all on Vdd, and split between Vss and Vdd) are available.
• I added a new class of termination with the termination resistor BEFORE the coupling capacitors. Both of the IBM drivers (LVDS and LVPECL) showed anomolous behavior when AC-cooupled. Source termination (100ohms between pads) improved both, but at the cost of reducing the signal amplitude and Vhyst by half. Placing the coupling capacitors after the termination restored normal behavior without reducing the amplitude. The calculated coupling capacitor for these cases is very small, so generally I only simulated the "High Frequency" case with a 1000pf coupling capacitor.
• The "On-Chip" coupling option will not include the low-pass filter in the test Receiver, and the Thp for the "Low Frequency" simulations will be set to the Tlp calculated per Chapter 6.

The Simulation Model and Nomenclature shows schematics of the test case (channel and Test Receiver) and the location and names of all of the various nodes, option switches, and defect switches. Use this for understanding the HSPICE deck and the simulation results.

These simulations include plots for both the board channel and the Test Receiver. The plots for the board channel include the driver input, both driver pads, both receiver pads, and the receiver output. (The recovered Vcom is also plotted for some DC simulations.) The plots for the Test Receiver include the difference voltage seen by each of the Test+, Test- and Testd comparators, and the set and reset pulses to the storage element.

The LVPECL, and LVDS models are from the IBM SA-12E 2.5V, .25-micron ASIC technology. There may be protocol specific additions to the model, and those will be described below. All these simulations include 10Kohm bias resistors from Vtt to Rx1+ and Rx1-.

The Bipolar CML simulations used AMCC drivers and real hysteretic comparators instead of the Test Receiver.

The test frequency is 5MHz (200ns cycle time, Ttest=100ns). For high frequency simulations the coupling capacitor is set to 20nf (Thp=1000ns), and for low frequency simulations the coupling capacitor is set to the minimum value calculated per Chapter 6, or .2nf (Thp=10ns). The older High frequency simulations are run for 10,000ns, and the last 700ns (approximately) are plotted, to allow initial conditions to die out. the older Low frequency and DC-coupled simulations are run for 1000 ns and the last 700ns (approximately) plotted. All timings can, of course, be scaled with the net RC.